TORONTO — Micron Technology touted its use of replacement gate (RG) technology for its latest 3D NAND flash memory, which it said is the first 176-layer NAND shipping in volume, while other players are focused on 128-layer NAND.
Eschewing floating gate in favor of a charge trap approach and combining it with its CMOS-under-array architecture enables Micron to significantly improve performance and density, said Derek Dicker, corporate vice president and general manager of Micron’s storage business unit. The company’s 176-layer NAND improves both read latency and write latency by more than 35% compared with the company’s previous generation of high-volume 3D NAND and a layer count that is nearly 40% higher than its nearest competitor.
While the layer count is higher, he said, the die size is approximately 30% smaller, which makes Micron’s 176-layer NAND ideal for small form factor use cases, including growing opportunities in 5G, artificial intelligence (AI), cloud and the intelligent edge for mobile storage, autonomous systems, and in-vehicle infotainment — the company has a large share of the overall automotive memory market. Dicker said a key characteristic of the new NAND is enhanced Quality of Service (QoS), which enables faster launching and switching across multiple apps in 5G smartphones to allow for full use of low-latency networking and true multitasking.
This is Micron’s second-generation replacement-gate architecture and fifth generation of 3D NAND, featuring a maximum data transfer rate at 1,600 megatransfers per second (MT/s) on the Open NAND Flash Interface (ONFI) bus, which translates into faster system boot up and application performance, said Dicker. This means near instant-on response times for automotive applications such as in-vehicle systems that will boot up as soon as the engine is started. The 176-layer 3D NAND is already shipping in its Crucial line of consumer SSDs, with enterprise SSDs to follow.
Micron’s 3D replacement-gate NAND flash storage creates a cell-to-cell approach that is closer to an interaction-free structure that uses a nonconductive layer of silicon nitride acting as a NANO storage cell to trap electrical charges. This layer surrounds the inside of the control gate of the cell, functioning as an insulator that stores charges. At the same time, Micron’s fabrication techniques mean that it is able to squeeze 176 layers into the same height that it has previously squeezed 64 layers through with high-aspect ratio etching, which create holes that are filled with metal to form vertical connections between layers of memory cells.
Gregory Wong, principal analyst with Forward Insights, said Micron’s ability to execute on this technology puts the company three to six months ahead of everyone else. “Everybody’s ramping 128-layer, but it’s kind of a stub node.” He doesn’t expect there to be huge volumes of 128-layer 3D NAND and expects Micron’s 176-layer will carry the company through to 2022.
Micron’s strategy is reminiscent of how it caught up on planar NAND after being behind on 2D nodes, by skipping 40 nanometers and going directly to 34 nanometers, said Wong. “That basically helped them catch up with the industry in terms technology. They’re trying to do something similar here and trying to get ahead.” Getting to 1,600 megatransfers per second is significant because it’s ahead of everyone else, he said, but others will catch up.
There are drawbacks to more layers, however, as one of the ways to build higher is to make the layers thinner, said Wong. “When you add the Z dimension, each layer of the Z dimension is thinner, but that has a negative impact on the reliability.” Skipping 128-layer does allow Micron some cost advantages, he said, but it’s spending money to transition from floating gate to its charge trap RG architecture. “They have to invest in that transition.”
However, it’s a move that makes sense for Micron, said Wong, because it has such broad range of flash-based offerings, unlike Intel, which recently sold its NAND business to SK Hynix, but it was only putting flash in SSDs. The advantage of the RG architecture is performance in part because the programming can be done in one step, unlike floating gate, where interference between memory cells requires multiple steps. This is fine for a large capacity device, such as an SSD, because there can be writing in the background, but it’s a disadvantage in smaller capacities where performance is critical, such as smartphones.
Wong said floating gate isn’t going away anytime soon because its reliability and retention is superior to charge trap, and SK Hynix will likely continue to run it to make SSDs as it has several generations left. If they do switch over, it will take quite an investment. But as a broader-based supplier, Micron must do more for the high-performance applications in AI, 5G, and automotive, he said. “Floating gate is really a disadvantage in those applications, and you don’t want to do both because it’s a lot of engineering resources.”
Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.
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