November 28, 2020

Improving Performance, Reducing Cost Through Host-Based ECC

4 min read
Cost pressures in memory-intensive applications such as high-end consumer products, networking, and industrial systems are...

Cost pressures in memory-intensive applications such as high-end consumer products, networking, and industrial systems are driving engineers to find new ways to reduce system cost while still improving performance. Error code correction (ECC) is an essential technology for maintaining reliability and extending memory longevity in NAND flash. To achieve better efficiency for these markets in NAND flash-based systems, developers continue to use architectures in which ECC is implemented in the host MCU, as opposed to those with integrated ECC. This article will explore the differences in integrated and host-based ECC, diving into the details of the impact of each approach on system performance, reliability, and ultimately cost.

Error Code Correction Technology
When selecting flash memory for a system, developers have the choice between NAND and NOR technologies. A NAND cell is smaller than a NOR cell, so NAND has a lower cost per bit than NOR memory. This in turn has led to NAND flash being available in higher densities compared to NOR flash. Furthermore, the physics behind the NOR cell results in a longer program-erase (P/E) time compared to NAND. Due to these advantages, NAND is being adopted at an ever-increasing rate.

The disadvantages of NAND flash have traditionally been its endurance and slower read performance. NAND cells wear down or lose their ability to hold a programmed value over time, causing memory bits to switch states. When a block begins experiencing wear, its data can be transferred to another block. To prevent data loss as cells degrade, ECC technology is used.

ECC uses redundancy to verify that stored data matches what was written to memory. In addition, when an error is detected, ECC can correct a limited number of errors per block to guarantee higher data integrity. When a certain error threshold is exceeded, the data is moved to a new block. The abandoned block is marked as “bad” and never used again. Thus, NAND flash combined with ECC can provide the level of integrity required by high-reliability applications.

However, because ECC generation and checking is a process that takes time, it impacts throughput and system cost, depending upon how it is implemented. In general, ECC can be integrated with the memory itself or managed externally by the host processor. Figure 1 shows the various implementation options. The integrated approach has two configurations: a one-die approach where ECC is part of the memory die and a two-die approach where a controller IC (with serial interface and ECC) is collocated with the memory die. With a host-based approach, ECC support is part of the MCU NAND flash controller accessing the NAND flash. The availability of these three options from memory manufacturers allows OEMs to select the best tradeoffs for their application.

Figure 1: With a host-based approach, ECC support is part of the MCU accessing the NAND flash. NAND Flash with integrated ECC is available as a one-die and two-die approach. The availability of these three options allows OEMs to select the best tradeoffs for their application. (Image source: Macronix)

A Flexible Approach to ECC
ECC integrated into the NAND flash memory offers the advantage that ECC is managed directly by the memory chip itself. However, while this simplifies system design to some degree, the integrated approach comes at the tradeoff of higher memory cost and reduced read performance. The reduced read performance is due to slower internal clocks in the flash, compared to much higher internal clock frequencies used in host processors.

Memory cost is higher because integrating ECC increases the size and complexity of the NAND flash device. Consider that a hardware implementation of 8-bit ECC has a gate count of about ~50K. This represents an ~1.7% impact on a simple memory controller’s gate count (3000K). If integrated on a NAND memory, however, the impact is between 10-15% and raises the cost of the memory more significantly. For systems with large memory requirements that use multiple memory devices, integrating ECC with the NAND memory means this added cost is paid multiple times, as opposed to paying for ECC a single time when it is based in the host MCU.

Read performance also drops because integrated ECC adds latency to each memory read at a clock rate lower than that at which a host controller could process ECC checking. Figure 2 shows a comparison of read throughput for NOR flash, NAND flash with integrated ECC, and NAND flash with host-based ECC. As can be seen, NAND flash with integrated ECC has less than half the performance of NOR flash. However, when ECC is host-based, NAND flash read performance nearly doubles, putting it almost on par with NOR flash.

Figure 2: NAND flash with integrated ECC has less than half the performance of NOR flash. However, when ECC is host-based, NAND flash read performance nearly doubles, putting it almost on par with NOR flash. (Image source: Macronix)

Host-based ECC also provides better performance when an error is detected (and corrected). Figures 3a and 3b show the impact of an error on the Read First Data Time (RFDT). With integrated ECC, RFDT increases from 45 to 70 microseconds. With host-based ECC, RFDT is much better, only increasing from 35 to 45 microseconds.

Figure 3a: With integrated ECC, the impact of an error on Read First Data Time (RFDT) increases from 45 to 70 microseconds. With host-based ECC, RFDT is much better, only increasing from 35 to 45 microseconds. (Image source: Macronix)

The post Improving Performance, Reducing Cost Through Host-Based ECC appeared first on EETimes.

Source link

Copyright © All rights reserved. | Newsphere by AF themes.