November 28, 2020

Explainer on Packaging: Interposers, Bridges and Chiplets

8 min read
EE Times recently sat down with Ramune Nagisetty, Intel’s packaging maven, to discuss the progress...

EE Times recently sat down with Ramune Nagisetty, Intel’s packaging maven, to discuss the progress in advanced packaging technologies in recent years, and where Intel sees them going in the future. Here’s what we learned.

The IC industry is clearing its path forward by relying on what was once one of its most mundane tools: packaging. There are several relatively new approaches to IC packaging, and they can all help significantly boost IC-level performance. The great thing is that many of these technologies are mature enough and have been around long enough that they are now accessible to even startups and universities.

While some of these technologies are already being offered by major foundries, one of the newest and most promising — chiplets technology — is still immature. What’s missing that would help advance the state of the art, says Intel’s Ramune Nagisetty, would be the creation of more standardized interfaces for mixing and matching the silicon components in advanced packages.

“The exciting part is lowering the barriers to play in this ecosystem,” she said. “Ten years from now, we’ll see fruits of this approach.”


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Nagisetty is Intel’s packaging maven; her formal title is director of process and product integration at Intel Technology Development. Intel, one of the last bastions of advanced semiconductor process technology in the U.S., has designated advanced packaging technology as one of the keys to its future. In a recent conversation with EE Times, Nagisetty said Intel has a technology roadmap for every one of its packaging vectors, just as it has always had roadmaps for process technology.

Ramune Nagisetty (Source: Intel)

Packaging was long the least glamorous aspect of the semiconductor business, but about 15 years ago it started becoming apparent that packaging could become a performance bottleneck, but with a bit of innovation, not only could that bottleneck be avoided, but new packaging approaches could actually enhance IC performance.

Intel has been doing this for a while now. The company proposed its Embedded Multi-die Interconnect Bridge (EMIB) technology in 2008 as a way to provide high density interconnect of heterogeneous chips; the company has been using it since 2011, Nagisetty observed.

EMIB is a variant of 2.5D technology. The common approach to 2.5D packaging is to use a silicon interposer – a layer of silicon with vias that is sandwiched (or “interposed”) between two chips. Intel believes interposers are often physically too large, so its EMIB uses a bridge die with multiple routing layers.

“New technologies need a tipping point before they start getting used,” Nagisetty said. “The inflection point was the rise of disruptive AI architectures based on neural networks.” And it wasn’t just the trend, but a specific event, the ImageNet competition in 2012. “That was an important point – it showed the feasibility of neural networks, and it gave rise to accelerators and high bandwidth memory inside the package – that began the toehold of memory in the package,” she said.

Historically, the general trajectory of the semiconductor industry has been to integrate more and more functions on-chip, but for some advanced IC designs, that was not recommended or not possible.

First, it’s not always possible for a company to put all the circuitry necessary from some applications on one giant die because from a production standpoint, the maximum size of a die is reticle-limited.

“The second point that drives this is the rising design cost for re-use and the need for IP portability for a particular technology node,” Nagisetty noted. “Logic technologies are becoming more specialized, whether for mobile or high performance.” The example she gave was a SerDes; there little if any need to implement a SerDes at the same technology node as the logic in advanced IC designs. More to the point, it’s possible to tailor a technology (e.g., a SerDes) to a technology node.

The SerDes example specifically references Intel’s Stratix FPGAs. Nagisetty said there is a menu of Stratix FPGAs, implemented at six different technology nodes available from three different foundries. “I think Stratix was first with 6 gigabit per second SerDes,” she said. “It allowed us to be more competitive and first to market with the high-speed SerDes.”

In short, there’s a benefit to disaggregation.

The third reason to embrace advanced packaging is to gain agility and flexibility, she said. “The value of mixing and matching chiplets from different technologies is becoming clear.”

Two really good examples, Nagisetty said, are Intel’s Kaby Lake G and Lakefield products.

“With Kaby Lake G we integrated third-party IP inside our package, which allowed us to create a smaller form factor for high performance mobile gaming.” The third-party IP was a Radeon accelerator from AMD.

That was a clear example of using advanced packaging to improve end-use performance, she said.

Where Kaby Lake G used Intel’s EMIB 2.5D approach, Lakefield relies on die stacking – 3D stacking. Intel calls its version of 3D stacking Foveros.

Intel’s Foveros technology

Lakefield, she said, is “an example of how packaging can give you the smallest X-Y footprint. The end user can see the benefit either in the performance or form factor, or both.”

There is a rich set of packaging technologies, and to make things even more interesting, they can be mixed-and-matched. Intel, for example, recently introduced “co-EMIB,” which is a combination of EMIB and Foveros.

Last year Intel introduced two more advanced packaging variations, omni-directional Interconect (ODI), which from an architectural standpoint is a stacking approach that allows for cantilevering chips. There are several benefits including power delivery to the top die in the stack through through-silicon vias (TSVs).

Intel, TSMC and others are working on an approach called copper-to-copper hybrid bonding, yet another variation of stacking that might lead to innovations in 3D ICs and the connecting of so many DRAM chips the combination is being referred to as DRAM cubes.

We asked Nagisetty if there are clear paths for continuously refining these packaging technologies, similar to the way successive production process nodes have always been plotted out.

“There is a packaging technology roadmap for every single one of our packaging vectors,” she responded. “So, we have one for interposer, one for decreasing pitch from 55 microns, going to 36 microns. And 36 is not where we end. Foveros will go to 25. Hybrid bonding will start at 10 and move down in pitch.”

The disaggregation, and associated examples such as Kaby Lake G, have sparked dreams among chip designers of mixing and matching functions from different suppliers – not just one. That’s the key concept of chiplets.

From a commercial standpoint, the chiplets approach makes a lot of sense. The cost of a highly integrated system on a chip (SoC) can be very high — so high it’s prohibitive for many. Furthermore, the complexity of such highly integrated semiconductor systems makes manufacturing more challenging; there is a direct relationship between higher complexity and yield loss.

The U.S. Department of Defense is interested for those reasons and others. The Defense Advanced Research Projects Agency (DARPA) is supporting a program to encourage the market for chiplets. This is DARPA’s take on the technology:

The monolithic nature of state-of-the-art SoCs is not always acceptable for Department of Defense (DoD) or other low-volume applications due to factors such as high initial prototype costs and requirements for alternative material sets. To enhance overall system flexibility and reduce design time for next-generation products, the Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS) program seeks to establish a new paradigm in IP reuse.

Turning to chiplets can significantly reduce cost, compared to a more complex SoC. This graphic was presented by AMD’s Lisa Su in a paper delivered at the IEDM conference in 2017 and reproduced by the Open Compute Project.

[There are two distinct programs using the acronym CHIPS. They are separate, but exacerbating possible confusion, they are congruent. Congress has proposed a bill called the Creating Helpful Incentives to Produce Semiconductors for America Act. The CHIPS for America Act does allocate funding specifically for advanced packaging research, but it does not specifically mention DARPA’s CHIPS program.]

Intel is, of course, participating in DARPA’s CHIPS program. “The Stratix FPGA is sort of the hub of that,” Nagisetty noted.

The key to success – of the CHIPS program specifically and of chiplets technology in general – is going to be the creation of more standardized interfaces so that chiplets from other companies can be connected.

To that end, Intel has contributed an interconnect technology called the advanced interface bus (AIB), which the company created in 2018. Starting in 2019, Intel has been making AIB available with a royalty-free license. (It can be found on GitHub.)

“This is the seed and toehold of what I believe will develop into an ecosystem, and innovation will be unlocked,” Nagisetty said. “It will be similar to the way boards developed –where have things like PCI Express – that allows companies to build products based on an interface standard.”

It’s early days, and there’s a lot of complexity to deal with, and also business models that need to be worked out,” she continued, “but what I love about it is that people can participate in this ecosystem. Before, the barrier was really high. But now, there are some startups and universities participating.”

Still, a body helping to shepherd the creation of standards around chiplets technology would be not just useful, but “critical,” Nagisetty said. “If I could fast-forward in time, this would be taken care of. AIB has been the best so far, but there’s more to be done. That’s where I would wish for more effort.”

One organization that is taking its first tentative steps toward filling that void is the Open Compute Project (OCP), which has a fledgling program proposing the development of an open domain specific accelerator (ODSA).

The Open Compute Project (OCP) says the conclusion from this projection from IHS Markit is that there is an “Immediate opportunity for chiplets and an open interface.” [Click directly on the graph for a larger view.]

It might not be immediately obvious how a group concerned directly with data center server technology gets so intimately involved with chiplets. The OCP starts with the observation that there will be an ongoing proliferation of new workloads that data centers will have to handle. Currently, the best solution for optimizing silicon systems for any given new workload is to create an SoC. But – as noted above – that gets expensive. One way of reducing the cost of silicon systems for emerging workloads would be to use chiplets technology – and that’s how the OCP gets involved with chiplets.

Today, different companies exploring chiplets technology tend to rely at least in part on  internally-developed design tools, and all chiplets interfaces are proprietary, according to the OCP. “ODSA seeks to democratize this evolution of chiplet and SIP [system in package] technology for the larger mass market through an open eco-system marketplace,” according to an OCP document called Intro to ODSA, which can be accessed from this page.

The post Explainer on Packaging: Interposers, Bridges and Chiplets appeared first on EETimes.

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