April 18, 2021

Deca Technologies — Part 2: Adaptive Patterning

6 min read
The conversation with Deca Technologies CTO Craig Bishop wrapped up the last column about at...

The conversation with Deca Technologies CTO Craig Bishop wrapped up the last column about at the discussion of moving to panel-level processing. That got us up to speed on the history of the company.

The history of Deca provided by Craig Bishop was excellent, but his personal passion is more forward-looking. Bishop was brought on board to develop something called “adaptive patterning.”

Once Deca divested its manufacturing operation in the Philippines (to Korea’s Nepes), more effort could be focused on developing the panel-level processing, especially improving patterning.

Adaptive patterning

It may not be difficult to imagine a few challenges for wafer-level packaging as it moves from the 300mm reconstituted wafer size to become panel-level packaging (PLP) at 600mm square.

Perhaps one of these might be obvious even for a smaller area, and that is die placement. In the Deca process flow, die are placed first and then a redistribution layer (RDL) is added to provide connections from the input and output pads on the die to the pads that can accept the solder balls that are sized to enable the packaged IC to be assembled into a system with larger dimensions.

Deca develops technology to drive the transition to 600mm panels (source: Deca Technologies)

The Deca M-series flow places die prior to forming the RDL. The other option is to create the RDL patterns on a carrier prior to attaching the singulated integrated circuit die.

Both approaches typically require high accuracy die placement. The mask patterns of the chip first flow require very tight alignment to the chips. Since the panels are square, the math gets simpler. 12,000 packages 6mm by 6mm can fit on one pane. That is a lot of very careful placement, and that comes at a high cost of both tooling and reduced throughput to achieve the accuracy. It compounds into the cost per component.

Conversely in the chip last flow, one is less constrained in the original patterning of RDL since the staring point is a clean slate of a carrier. However, chip placement must match the I/O pads to their respective locations on RDL with comparable accuracy to the chip first packaging flow.

High precision die attach is easily the largest portion of capital outlay for panel level process. Deca estimates it to be just over 18%. In their adaptive patterning systems, this drops to the lowest contributor to tooling expense at just over six percent.

Adaptive patterning
Adaptive patterning reduces cost for die attach (source: Deca Technologies. Click on the image for a larger view.)

To increase throughput and reduce the cost of die placement, the Deca approach is to use a chip shooter. This is the highest speed, lowest accuracy solution available. Whereas a flip chip bonder provides better than 10µm accuracy, the chip shooter is only in the ± 20µm range. But it can pile the chips on at 28,000 per hour for a two-headed, 20 nozzle per head tool. As we saw in Part 1, Deca leveraged tooling from printed circuit board (PCB) manufacturing.

Chips are placed, but not ideally. What next?

The answer is maskless lithography by laser direct patterning. Deca touts themselves as the fist packaging company to use this technology that they scaled down from PCB manufacturing.

The assumption is that the exact location of I/O pads on the chip is unknown. The system locates the die after they are attached to a carrier substrate. the Deca system performs a high speed scan to map the target locations. A design software system than adapts the random locations to create RDL patterns that move to accomodate them.

Die pads are randomly located or at least not precisely aligned to fixed point. The package ball pattern has a specification and each ball site has a fixed location to meet the spec.

Something has to give.

The first attempt is to change the trace routing from BGA pad to I/O pad. That may do the trick. If not, the constraint on a package solder ball pad is a lot looser than for a chip pad that is at least an order of magnitude smaller. The BGA pad can also be shifted if necessary. These two adaptations allow chip placement tools with reduced placement accuracy of up to ±25µm rather than conventional mask-based RDL patterning requiring down to ±2µm.

One point to keep in mind comparing this approach to one in which die are placed as accurately as possibly is the effect of the encapsulation process. The liquid epoxy mold compound will affect final die position through the curing process. Adaptive patterning easily handles this positional error.

adaptive patterning throughput
Throughput and cost per unit comparison of die placement options (source: Deca Technologies)

Like with most new approaches to old problems, there is some convincing that needs to happen. For engineers that have carefully designed and simulated the routing to include sensitive electromagnetic and other effects, you might expect outright shock and dismay that the traces could shift during manufacturing.

I asked Craig whether the analog and RF people would even entertain this idea.  For high speed digital signalling, Craig Bishop assures us that the substrate variation completely swamps any effect introduced by adaptive patterning.

In Bishop’s words, “Designers have to know going in.”

10X thinking

Of course, everything in the engineering world of tradeoffs comes at a cost. Deca adaptive patterning is straining data throughput to improve manufacturing throughput.

Since the die and each pad location have to be mapped, keeping things moving through production means getting images acquired and processed quickly.

It’s a big challenge. The full panel needs to be imaged and those images processed for identification of the target I/O pads. The system will then design the routing to correctly match the physical positions of the pads.

The adaptive patterning system holds a single design file for a full 300mm wafer. A new one is designed and exposed every 28 seconds.

It’s more data, but this scales quite easily to 600mm panels, at least compared to all the mechanical design and handling. Moving up to 600mm means processing 257 Gigapixels per second. The data handling system Deca created will handle up to 2.8 terabytes of data every minute.

Enabling the chiplet age

Cost drove the innovation to relax chip placement constraints, but adaptive patterning may now drive the transition to chiplets. After all, if there was a challenge to a panel of only one type of die, mixing and matching to create systems in a package is definitely a step beyond.

With wafer process technology facing what are turning out to be intractable issues with scaling, the new mantra is “More than Moore” or MTM. Integration and scaling must now take place beyond system-on-chip design, and we need to look outside the wafer fab.

This animation illustrates the movement of traces to accommodate the “chip shooter.”

The adaptive patterning gave a pathway to 600mm by moving significant costs out of the way. Now, it can also continue to drive the industry scaling trends by driving chiplets into wider production. Deca believes the true power of their second generation systems will do just that.

On that path, Deca has demonstrated panel-level packages integrating nine chiplets through a system of three levels of RDL.

It isn’t hard to realize what the scalability of the very large panel package processing of highly integrated chiplet designs will achieve in the context of what we have already seen.

Despite the design and manufacturing constraints, AMD charged ahead with chiplet designs using a conventional substrate approach. By most accounts, AMD seems to have been successful with their chiplet approach on two generations of chiplet microprocessors.

There are advantages to transitioning away from system-on-chip some to the chiplet format. And that would be under normal circumstances. The world hasn’t been normal for a while, and it is less so in the semiconductor business.

Advanced node availability is a problem for any customer outside the top two. Big fabless companies see a lot of risk even being the number two wafer consumer of a foundry.

As Craig Bishop sees it, companies are more or less being forced into chiplets. The supply chain crunch is accelerating the transition.

Going back to AMD for a minute, chiplets can be integrated onto advanced substrates, but Bishop noted that a supply chain issue currently exists for substrates as well.

Deca panel level processing and the flexibility offered by their novel adaptive patterning technique appears ready to accelerate the chiplet revolution. Deca’s choice of tools and materials for their process should keep things running smoothly. But in the age of Covid-19, one can never be too sure what supply chain will be infected next.

The post Deca Technologies — Part 2: Adaptive Patterning appeared first on EETimes.

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